1. Technical Field
The present invention relates to a method and system for utilizing cache memories in general and, in particular, to a method and system for utilizing cache memories within a symmetric multiprocessor data-processing system. Still more particularly, the present invention relates to a method and system for enhancing cache memory utilization within a symmetric multiprocessor data-processing system.
2. Description of the Prior Art
In a symmetric multiprocessor (SMP) data-processing system, all of the processing units are generally identical; that is, they all have the same architecture and utilize a common set or subset of instructions and protocols to operate. Typically, each processing unit includes a processor core having at least one execution unit for carrying out program instructions. In addition, each processing unit may include at least one level of caches, commonly referred to as L1 or primary caches, which are implemented with high-speed memories. In most cases, a second level of caches, commonly referred to as L2 or secondary caches, may also be included in each processing unit for supporting the first level caches. Each level of cache stores a subset of the data and instructions contained in a system memory for low latency access by the processor cores.
Within an SMP environment, if a first processing unit contains a modified copy of data that is being requested by a second processing unit, the first processing unit does not send the requested data to a system memory for access by the second processing unit; instead, a cache-to-cache transfer of the requested data from the first processing unit to the second processing unit is performed. Upon receipt of the cache-to-cache transfer of the requested data, the second processing unit returns an acknowledgement of the receipt to the first processing unit. The process of transferring data from one processing unit to another processing unit on a system bus without going through a system memory is referred to as "intervention." An intervention protocol improves system performance by reducing the number of cases in which the high latency system memory must be accessed in order to satisfy a read or read-with-intent-to-modify request by any one of the processing units within the SMP data-processing system.
Because the latency associated with system memory access are generally quite large, apparently it would be advantageous to maintain as much useful data in at least one of the cache memories as possible to allow for intervention such that system memory access may be avoided. To that end, the present invention provides an improved method and system for enhancing cache memory utilization within a SMP data-processing system such that the frequency of system memory accesses is minimized.